Leakage current minimisation and power reduction techniques using sub-threshold design
- Tsague, Hippolyte Djonon, Twala, Bhekisipho
- Authors: Tsague, Hippolyte Djonon , Twala, Bhekisipho
- Date: 2015
- Subjects: Power dissipation , Weak inversion , Ultra-low-power , Leakage currents , Power analysis
- Language: English
- Type: Conference proceedings
- Identifier: http://hdl.handle.net/10210/18211 , uj:15971 , Citation: Tsague, H.D. & Twala, B. 2015. Leakage current minimisation and power reduction techniques using sub-threshold design. International Conference on Information Society (i-Society 2015), 9-11 November 2015, London UK. p. 146-150.
- Description: Abstract: Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and radio frequency identification bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to re- charge the batteries while at the same time dramatically decreasing the device leakage currents. The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices. In this research, a SOI device was built to compare their electrical characteristics using Silvaco software. The comparisons were focus! ed on three main electrical characteristics that are threshold voltage, sub-threshold voltage and leakage current. It was found that SOI devices are ideal candidates for low power operation.
- Full Text:
- Authors: Tsague, Hippolyte Djonon , Twala, Bhekisipho
- Date: 2015
- Subjects: Power dissipation , Weak inversion , Ultra-low-power , Leakage currents , Power analysis
- Language: English
- Type: Conference proceedings
- Identifier: http://hdl.handle.net/10210/18211 , uj:15971 , Citation: Tsague, H.D. & Twala, B. 2015. Leakage current minimisation and power reduction techniques using sub-threshold design. International Conference on Information Society (i-Society 2015), 9-11 November 2015, London UK. p. 146-150.
- Description: Abstract: Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and radio frequency identification bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to re- charge the batteries while at the same time dramatically decreasing the device leakage currents. The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices. In this research, a SOI device was built to compare their electrical characteristics using Silvaco software. The comparisons were focus! ed on three main electrical characteristics that are threshold voltage, sub-threshold voltage and leakage current. It was found that SOI devices are ideal candidates for low power operation.
- Full Text:
Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs
- Tsague, Hippolyte Djonon, Twala, Bhekisipho
- Authors: Tsague, Hippolyte Djonon , Twala, Bhekisipho
- Date: 2015
- Subjects: Cryptographic keys , Side channel , MOSFET , Biaxial , Strained , Silicon , Leakage currents , Sub-threshold voltage , Encryption
- Language: English
- Type: Conference proceedings
- Identifier: http://hdl.handle.net/10210/18137 , uj:15963 , Citation: Tsague, H.D. & Twala, B. 2015. Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs. Fifth International Conference on Digital Information, Processing and Communications (ICDIPC2015), October 7-9, 2015, Sierre, Switzerland. p.38-43. ISBN: 978-1-4673-6832-2
- Description: Abstract: Although cryptography constitutes a considerable part of the overall security architecture for several use cases in embedded systems, cryptographic devices are still vulnerable to the diversity types of side channel attacks. Improvement in performance of Strained Silicon MOSFETs utilizing conventional device scaling has become more complex, because of the amount of physical limitations associated with the device miniaturization. Therefore, a great deal of attention has recently been paid to the mobility improvement technology through applying strain to CMOS channels. This paper reviews the characteristics of strained-Si CMOS with an emphasis on the mechanism of mobility enhancement due to strain. The device physics for improving the performance of MOSFETs is studied from the viewpoint of electronic states of carriers in inversion layers and, in particular, the sub-band structures. In addition, design and simulation of biaxial strained silicon NMOSFET (n-channel) is done using Silvaco’s Athena/Atlas simulator. From the results obtained, it became clear that biaxial strained silicon NMOS is one of the best alternatives to the current conventional MOSFET.
- Full Text:
- Authors: Tsague, Hippolyte Djonon , Twala, Bhekisipho
- Date: 2015
- Subjects: Cryptographic keys , Side channel , MOSFET , Biaxial , Strained , Silicon , Leakage currents , Sub-threshold voltage , Encryption
- Language: English
- Type: Conference proceedings
- Identifier: http://hdl.handle.net/10210/18137 , uj:15963 , Citation: Tsague, H.D. & Twala, B. 2015. Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs. Fifth International Conference on Digital Information, Processing and Communications (ICDIPC2015), October 7-9, 2015, Sierre, Switzerland. p.38-43. ISBN: 978-1-4673-6832-2
- Description: Abstract: Although cryptography constitutes a considerable part of the overall security architecture for several use cases in embedded systems, cryptographic devices are still vulnerable to the diversity types of side channel attacks. Improvement in performance of Strained Silicon MOSFETs utilizing conventional device scaling has become more complex, because of the amount of physical limitations associated with the device miniaturization. Therefore, a great deal of attention has recently been paid to the mobility improvement technology through applying strain to CMOS channels. This paper reviews the characteristics of strained-Si CMOS with an emphasis on the mechanism of mobility enhancement due to strain. The device physics for improving the performance of MOSFETs is studied from the viewpoint of electronic states of carriers in inversion layers and, in particular, the sub-band structures. In addition, design and simulation of biaxial strained silicon NMOSFET (n-channel) is done using Silvaco’s Athena/Atlas simulator. From the results obtained, it became clear that biaxial strained silicon NMOS is one of the best alternatives to the current conventional MOSFET.
- Full Text:
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