Abstract
Reduction of circulating current is one of the major considerations in inverter
fed electrical drives. Diode clamped MLI enables higher output current per
phase, thereby rating of the drive gets increased effectively. Various methods
of triggering in the inverter legs creates better voltage profile and leads to the
enabling of circulating current in the drive system. The induced circulating
current flows through the apparatus neutral (N) and supply ground (G) is
caused by the existence of parasitic capacitance. This circulating current may
cause potential danger especially when parasitic capacitance poses large. In
the past, different modulation techniques and conversion topologies have
been introduced to minimize the flow of circulating current. However, these
techniques lead to complexity, high cost, low voltage profile and efficiency
due to lower modulation parameters. This paper proposes PS, POD, PD
carrier shifting PWM algorithms for diode clamped MLI to tumbling the
circulating current within the each phase of inverter legs. The performances
of proposed algorithm, in terms of circulating current, THD, losses and
efficiencies are analyzed theoreticallyand are validated via simulation and
experimental results.