Abstract
With its unique characteristics of scaling, low power consumption, and noise immunity, Complementary Metal Oxide Semiconductor (CMOS) technology has become the ideal candidate for applications in the Image Detector Market. This market has shown one of the largest compound annual growth rates of all electronic sectors. From smartphones and security systems to self-driving cars, CMOS Image Detectors (CID) are transforming our world by capturing visual information with ever-increasing accuracy and speed.
CMOS Active Pixel Sensors (APS) are the preferred choice for CIDs due to their notable benefits, including on-chip integration capabilities, low power consumption, low voltage operation, and the suppression of noise generated or injected into the signal readout path. However, these devices still suffer from non-linearities in the pixel reading, which cause distortions in the final output signal. These distortions, manifesting as noise in the reconstructed image, reduce the accuracy of the image data and, consequently, the overall image quality.
The research investigated whether the overall performance and sensitivity of a Three Transistor (3T) CID could be improved by replacing the existing Reset Transistor (M1) with three different circuit components at varying Aspect Ratios (AR) and/or Equivalent Resistance Ratios (ERR). These components resulted in three modified 3T CID circuits: a circuit with a standard passive resistor (R1) in place of M1, a PMOS transistor (P1) in place of M1, and a MOSFET active load (AL1) circuit in place of M1. Each circuit was simulated in LT SPICE, using models created from the SG13G2 PDK, an open-source 0.13 μm SiGe BiCMOS process from IHP.
Each circuit simulation produced four plots at the varying ARs: DC Sweep, Transient Analysis, Output Noise, and Frequency Response. These plots were analysed in detail, and the modified circuits were then compared to the original 3T circuit. A linearity analysis was conducted using both linear and exponential regression (R) on the DC sweep data, and a sensitivity analysis was performed using differential sensitivity from the DC sweep data. A performance analysis was conducted between the original 3T CID and the modified CIDs using RMS Noise, Bandwidth (BW), Power Bandwidth (P_BW) and Gain values extracted from LT SPICE noise and frequency response plots. Further, the signal-to-noise ratio (SNR) is calculated from the transient response and output noise plots. The linearity, sensitivity and performance analysis results were used to make a conclusive statement regarding the optimisation of circuit
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In-Confidence
performance and responsivity. Furthermore, a fill-factor (FF) analysis was performed using a Python script algorithm to determine FF from the layout design done in KLayout of each modified circuit. The FF percentage change of the modified circuits was then compared to the original 3T circuit.
It was found that each circuit modification improved either performance and/or responsiveness, enhanced pixel sensitivity, and general pixel output linearity. The results indicated that replacing M1 with different circuit elements presents a viable option for future circuit improvements and enhancements that can be used in various applications.