Abstract
Abstract:
Although cryptography constitutes a considerable
part of the overall security architecture for several use cases in
embedded systems, cryptographic devices are still vulnerable to
the diversity types of side channel attacks. Improvement in
performance of Strained Silicon MOSFETs utilizing conventional
device scaling has become more complex, because of the amount
of physical limitations associated with the device miniaturization.
Therefore, a great deal of attention has recently been paid to the
mobility improvement technology through applying strain to
CMOS channels. This paper reviews the characteristics of
strained-Si CMOS with an emphasis on the mechanism of
mobility enhancement due to strain. The device physics for
improving the performance of MOSFETs is studied from the
viewpoint of electronic states of carriers in inversion layers and,
in particular, the sub-band structures. In addition, design and
simulation of biaxial strained silicon NMOSFET (n-channel) is
done using Silvaco’s Athena/Atlas simulator. From the results
obtained, it became clear that biaxial strained silicon NMOS is
one of the best alternatives to the current conventional MOSFET.