Abstract
Abstract:
This paper presents a comprehensive study of
leakage reduction techniques applicable to CMOS based devices.
In the process, mathematical equations that model the powerperformance
trade-offs in CMOS logic circuits are presented.
From those equations, suitable techniques for leakage reduction
as pertaining to CMOS devices are deduced. Throughout this
research it became evident that designing CMOS devices with
high-κ dielectrics is a viable method for reducing leakages in
cryptographic devices. To support our claim, a 22nm NMOS
device was built and simulated in Athena software from Silvaco.
The electrical characteristics of the fabricated device were
extracted using the Atlas component of the simulator. From this
research, it became evident that high-κ dielectric metal gate are
capable of providing a reliable resistance to DPA and other form
of attacks on cryptographic platforms such as smart card.The
fabricated device showed a marked improvement on the I on/I off
ratio, where the higher ratio means that the device is suitable for
low power applications. Physical models used for simulation
included Si3N4 and HfO2 as gate dielectric with TiSix as metal
gate. From the simulation result, it was shown that HfO2 was the
best dielectric material when TiSix is used as the metal gate.